Regviz

NXP Semiconductors /LPC408x_7x /ETHERNET /MWTD

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MWTD

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/NeoM3/ETHERNET/MWTD#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0WRITEDATA0RESERVED

Description

MII Mgmt Write Data register.

Fields

WRITEDATA

WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR).
RESERVED

Unused

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data